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5x7mm Surface Mount High Precision TCXO In Stock at Digi-Key
Description
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com US Headquarters 630-851-4722: European Headquarters: +353-61-472221
D7 The Connor-Winfield 's D75F 5 27 F 08 .0M 47 Series are 5x7mm Surface Hz Mount Temperature Compensated Crystal Controlled Oscillators (TCXO) with a Tri-State LVCMOS output. Through the use of Analog Temperature Compensation, the D75F - Series are capable of holding sub 1-ppm stabilities over the 0 to 70C temperature range.
Features
Model D75F
TCXO 3.3V Operation LVCMOS Output Logic Frequency Stability: 0.50ppm Temperature Range: 0 to 70C Low Jitter <1pS RMS Tri-State Enable/Disable Function 5x7mm Surface Mount Package Tape and Reel Packaging RoHS Compliant / Lead Free
Specifications
Absolute Maximum Ratings
Parameter Storage Temperature Supply Voltage Input Voltage (Vcc) Minimum -55 -0.5 -0.5 Nominal Maximum 85 6.0 Vcc+0.5 Units C Vdc Vdc Note
Operating Specifications
Parameter Frequencies Available Frequency Calibration @ 25 C Frequency Stability [(Fmax - Fmin)/2.Fo] Supply Voltage Variation (Vcc 5%) Load Coefficient (5%) Static Temperature Hysteresis Aging Temperature Range Supply Voltage Supply Current Period Jitter Phase Jitter (BW=12kHz to 20MHz) SSB Phase Noise at 10Hz offset SSB Phase Noise at 100Hz offset SSB Phase Noise at 1KHz offset SSB Phase Noise at 10KHz offset SSB Phase Noise at >100KHz offset (Vcc) (Icc) (Fo) -1.0 -0.5 -0.2 -0.2 -1.0 0 3.135 Minimum Nominal 3.3 3 0.5 -80 -110 -135 -150 -150 Maximum 1.0 0.5 0.2 0.2 0.4 1.0 70 3.465 6 5 1 Units MHz ppm ppm ppm ppm ppm ppm/year C Vdc mA ps rms ps rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 3 1 2 Note 13.0, 19.44, 25.0, 27.0
Input Characteristics For Enable / Disable Function (Pin 8)
Parameter Enable Voltage (High) or open circuit Disable Voltage (Low) Output Tri-stated (Vih) (Vil) Minimum 70%Vcc Nominal Maximum 30%Vcc Units Vdc Vdc Note 4
LVCMOS Output Characteristics
Parameter LOAD Voltage Current (High) (Low) (High) (Low) Duty Cycle at 50% of Vcc Rise / Fall Time 10% to 90%
Note: 1) 2) 3) 4) 5)
Minimum (Voh) (Vol) (Ioh) (Iol) 90%Vcc -4 45 -
Nominal 15 50 -
Maximum 10%Vcc 4 55 8
Units pF Vdc Vdc mA mA % ns
Note 5
Bulletin Page Revision Date
Tx237 1 of 2 01 14 Nov 2008
Initial calibration @ 25 C. Specifications at time of shipment after 48 hours of operation Frequency stability vs. change in temperature. Frequency change after reciprocal temperature ramped over the operating range. Frequency measured before and after at 25C. Leave Pad 8 unconnected if enable / disable function is not required. When tri-stated, the output stage is disabled but the oscillator and compensation circuit are still active (current consumption < 1 mA). or best performance it is recommended that the circuit connected to this output should have an equivalent input capacitance of 15pF.
Specifications subject to change without notice. All dimensions in inches. (c) Copyright 2008 The Connor-Winfield Corporation
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com
Package Characteristics
Package Ceramic Surface Mount Package.
Environmental Characteristics
Vibration: Shock: Soldering: Solderability Vibration per Mil Std 883E Method 2007.3 Test Condition A Mechanical Shock per Mil Std 883E Method 2002.4 Test Condition B. SMD product suitable for Convection Reflow soldering. Peak temperature 260 C. Maximum time above 220 C, 60 seconds. Solderability per Mil Std 883E Method 2003
Ordering Information D75F - 013.0MHZ * D75F - 019.44MHZ * D75F - 025.0MHZ * D75F - 027.0MHZ *
TCXO SERIES CENTER FREQUENCY
Design Recommendations
Vcc, should have a large copper area for reduced inductance. Connect a 0.01uF bypass capacitor <0.1"(2.54mm) from the pad.
8 9
6 5
0.010"(0.254mm) Recommended clearance inductance for internal copper flood. Ground, should have a large copper area for reduced inductance.
Buffer input load should be equivalent to 15pF. 50 Ohm trace Vcc <1"by design Buffer Ground Top View Ground
* For the tape and reel option, add -T to the end of the part number. Example: D75F-027.0 MHZ -T
Pad Connections
Pad 1 2 3 4 5 6 7 8 9 10 Connection Do not connect Do not connect Do not connect Ground Output Do not connect Do not connect Tri-state Enable / Disable Supply, Vcc Do not connect
10 1 3
4
Top View
OSC TOP LAYER GROUND LAYER
50 Ohm Trace Without Output Vias Buffer
Output Waveform
BOTTOM LAYER
Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane.
Package Layout
0.276 0.006 (7.0mm) 0.079 Max. (2.0mm)
D75F 0847 27.0MHz
Pin 1
.......
0.197 0.006 (5.0mm) 0.025(6 Places) (0.635mm) 0.040 (1.02mm) (6 Places)
Suggested Pad Layout
0.295 (7.49mm) 0.030 (0.76mm) 0.051 (1.28mm)
Test Circuit
E/D DNC DNC
8 Vcc Supply Voltage 9 10 DNC 1
7
6 5 4 Output
0.037 (0.94mm) 0.215 (5.46mm)
1
0.030 (0.762mm) (4 Places)
2
3 4
Top View 1
Keep Out Area*
.01 uF Bypass
2
3
15 pF**
10
0.100 (2.54mm)
9 8
0.038 (0.965mm) (4 Places)
7
6
5
0.051 (1.28mm)
DNC DNC DNC
0.100 (2.54mm)
Dimensional Tolerance: .005 (.127mm) .02 (.508mm)
Tape and Reel Information
* Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane.
DNC = Do Not Connect E/D = Enable / Disable ** NPO Grade component
Solder Profile
Temperature 260C 220C 180C 260C
1
150C 120C
0 120 S Max. Time 10 S 60 S Max. 360 Sec. Max.
US Headquarters: 630-851-4722 European Headquarters: +353-61-472221
Specifications subject to change without notice. All dimensions in inches. (c) Copyright 2008 The Connor-Winfield Corporation
Bulletin Page Revision Date
Tx237 2 of 2 01 14 Nov 2008

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